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  • 个人信息
    C. John Glossner

    C. John Glossner

    系      所:
    |计算机科学与技术系|
    职      称:
    教授  
    职      务:
    特聘教授
    办公地点:
    机电楼1201
    办公电话:
    电子邮箱:
    jglossner@ustb.edu.cn
    本 科 课 程:
    研究生课程:
    科 研 方 向:
    Computer Architecture Heterogeneous Computing Artificial Intelligence
    学术与社会兼职:
    IEEE Senior Member Tau Beta Pi (National Engineering Honor Society) Eta Kappa Nu (Electrical Engineering Honor Society) Golden Key Honor Society President, Heterogeneous System Architecture Foundation (HSA) Industry Executive, New York Institute of Techno
  • 简   历

     AWARDS

    1)    2014 Elected to China’s 1000 Talents.

    2)    2013 OST/Wuxi DSP named one of 100 fastest growing companies in China.

    3)    2012 Software Defined Radio Forum’s President’s Award for SDR accomplishments and contributions

    4)    2009 EE Times ACE Award Finalist.

    5)    2005 World Economic Forum’s 2005 Tech Pioneer award winner for developing a technology with the “potential to spark economic development worldwide”

    6)    2004 Software Defined Radio Conference Best Paper Award for Software Centric Approach to Developing Wireless Applications.

    7)    2003 Forbes 5th annual “E-Gang” top company winner.

    8)    2003 Entreprenuer Magazine the Big Guns - Getting Corporate Investors with Traditional VC's.

    9)    2002 Ernst & Young Entrepreneur of the Year finalist.

    10)  Significant press coverage of Sandbridge technology in The Wall Street Journal, Forbes, PC Week, The Economist, InStat, CNET News, Extreme Tech, Engadget, John Peddie’s Tech Watch, EDN, Dow Jones Venture Capital Analyst, Unstrung, Information Week, Wireless Web, and EE Times.

    EDUCATION

    Doctor of Philosophy (Ph.D.) in Electrical Engineering

    Delft University of Technology, Delft, The Netherlands

    Advisor: prof. dr. Stamatis Vassiliadis

    2001

    Department of Electrical and Computer Engineering. Research in parallel, vector and multithreaded processors. Thesis:

    Delft-Java – A Multithreaded Java Processor.

    Preliminary Ph.D. Studies

    The University of North Carolina, Chapel Hill, NC

    Advisor: Prof. Dr. Frederick P. Brooks, Jr.

    1994-1995

    Department of Computer Science. Research in computer architecture, parallel architecture, distributed computing,

    parallel languages, and graphics.

    Master of Science in Electrical Engineering (M.S.E.E.)

    The National Technological University (NTU), Fort Collins, CO

    1990

    Electromagnetics and VLSI subject focus.

    Master of Science in Engineering Management (M.S.E.M.)

    The National Technological University (NTU), Fort Collins, CO

    1989

    MSEM is a Master of Business Administration (MBA) for Engineers. International Business and joint ventures subject

    focus.

    Bachelor of Science in Electrical Engineering (B.S.E.E.)

    Penn State, State College, PA

    1985

    Semiconductor device physics and computer design subject focus.

    Honor Societies: Eta Kappa Nu (Electrical Engineering Honor Society), Tau Beta Pi (National Engineering Honor Society),

    Golden Key Honor Society.

  • 代表性论文

     [1].    D. Iancu, J. Glossner, G. Nacer, S. Stanley, V. Kolashnikov, and J. Hoane, “Software defined radio platform withwideband tunable front end”, International Journal of Engineering & Technology, 4(1) (2015) 97-103, SciencePublishing Corporation.

    [2].    S. Bang, C. Ahn, Y. Jin, S. Choi, J. Glossner, and S. Ahn, “Implementation of LTE system on an SDR platform using CUDAand UHD”, Journal of Analog Integrated Circuits and Signal Processing 78(3), March 2014.

    [3].    C. Ahn, S. Bang, H. Kim, S. Lee, J. Kim, S. Choi, and J. Glossner, “Implementation of an SDR system using an MPI-basedGPU cluster for WiMAX and LTE”, Journal of Analog Integrated Circuits and Signal Processing (2012) 73: 569-582 ,November 01, 2012.

    [4].    H. Yang, T. Kim, C. Ahn, J. Kim, S. Choi, and J. Glossner, “Implementation of parallel lattice reduction-aided MIMOdetector using graphics processing unit”, Journal of Analog Integrated Circuits and Signal Processing (2012) 73: 559-567 , November 01, 2012.

    [5].    C. Jenkins, M. Schulte, and J. Glossner, “Instructions and hardware designs for accelerating SNOW 3G on a softwaredefinedradio platform”, Journal of Analog Integrated Circuits and Signal Processing, December 2011, Volume 69,Issue 2-3, pp 207-218.

    [6].    J. Kim, C. Ahn, S. Choi, and J. Glossner, “Implementation of smart antenna API and transceiver API in softwarecommunication architecture for a wireless innovation forum standard”, Journal of Analog Integrated Circuits andSignal Processing, December 2011, Volume 69, Issue 2-3, pp 219-226.

    [7].    C. Jenkins, S. Mamidi, M. J. Schulte, and J. Glossner, “Instruction Set Extensions for the Advanced Encryption Standardon a Multithreaded Software Defined Radio Platform,” in International Journal of High Performance SystemsArchitecture 2(3), August, 2010.

    [8].    V. Surducan, M. Moudgill, G. Nacer, E. Surducan, P. Balzola, J. Glossner, S. Stanley, Meng Yu, and D. Iancu, “TheSandblaster Software-Defined Radio Platform for Mobile 4G Wireless Communications”, International Journal ofMultimedia Broadcasting, Guest Editors: Daniel Iancu, John Glossner, Mihai Sima, Peter Farkas, and Michael McGuire,Volume 2009, Article ID 384507.

    [9].    S. Mamidi, E. R. Blem, M. J. Schulte, J. Glossner, D. Iancu, A. Iancu, M. Moudgill, and S. Jinturkar, "Instruction SetExtensions for Software Defined Radio," in the International Journal on Microprocessors and Microsystems, vol. 33,no. 4, pp. 260-272, June 2009.

    [10]. E. Surducan, V. Surducan, D. Iancu, J. Glossner, “Multiband Antennas for SDR Applications”, International Journal ofDigital Multimedia Broadcasting, Volume 2009, Article ID 460143.

    [11]. S. Mamidi, E. R. Blem, M. J. Schulte, J. Glossner, D. Iancu, A. Iancu, M. Moudgill, and S. Jinturkar, “Instruction SetExtensions for Software Defined Radio,” in the Journal of Embedded Systems, 2007.

    [12]. J. Glossner, D. Iancu, M. Moudgill, G. Nacer, S. Jinturkar, S. Stanley, and M. Schulte, “The Sandbridge SB3011Platform”, EURASIP Journal on Embedded Systems, Volume 2007, Article ID 56467, 16 pages.

    [13]. M. J. Schulte, J. Glossner, S. Jinturkar, M. Moudgill, S. Mamidi, S. Vassiliadis, “A Low-Power Multithreaded Processorfor Software Defined Radio,” in the Journal of VLSI Signal Processing (Special Issue Featuring Extended Versions ofBest Papers from SAMOS2004), vol. 43, no. 2-3, pp. 143 – 159, June 2006.

    [14]. D. Iancu, J. Glossner, H. Ye, Y. Abdelila, S. Stanley, “Software AM Radio Implementation”, Journal of ElectricalEngineering, Vol. 54, No. 9-10, pages 273-276, 2003.

    [15]. E. G. Walters III, J. Glossner, and M. Schulte, “Automatic VHDL Model Generation of Parameterized FIR Filters”,Domain Specific Processors : Systems, Architectures, Modeling and Simulation, Lecture Notes in Computer Science, pp.1-17, January, 2004.

    [16]. J. Glossner, D. Iancu, J. Lu, E. Hokenek, and M. Moudgill, “A Software Defined Communications Baseband Design”,IEEE Communications Magazine, Vol. 41, No. 1, pages 120-128, January, 2003.

    [17]. J. Glossner, T. Raja, E. Hokenek, and M. Moudgill, “A Multithreaded Processor Architecture for SDR”, The Proceedingsof the Korean Institute of Communication Sciences, Vol. 19, No. 11, pp. 70-84, November, 2002.

    [18]. J. Glossner, M. Schulte, and S. Vassiliadis, “A Java-Enabled DSP”, in Embedded Processor Design Challenges, Systems,Architectures, Modeling, and Simulation (SAMOS), Lecture Notes in Computer Science 2268, E. Deprettere, J. Teich,and S. Vassiliadis editors, pp 307-325, Springer-Verlag, Berlin, 2002.

    [19]. J. Glossner, J. Thilo, and S. Vassiliadis, "Java Signal Processing: FFT's with bytecodes", Journal of Concurrency andExperience, vol. 10, No. 11-13, pages 1173-1178, October, 1998.

    [20]. W.F. Lawless, C.J. Glossner, and G.G. Pechanek, “Line Drawing using Mfast DSP Array Processor.” IBM TechnicalDisclosure Bulletin, Vol. 38, No. 08, pages 395-399, August, 1995. A parallel line rendering algorithm formultiprocessors.

    [21]. C.J. Glossner, “CMOS Open Drain Common I/O Test Methodology”. IBM Technical Disclosure Bulletin, Vol. 31, No. 5,pages 343-344, October, 1988.

    详见谷歌学术

  • 科研业绩
  • 获得奖励/专利

     [1].    M. Moudgill, C. J. Glossner, A. J. Hoane, P. Hurtley, and V. Kalashnikov, “Vector processor configured to operate on variable length vectors using implicitly typed instructions”, 9,959,246. Issued to Optimum Semiconductor Technologies, Inc. May 1, 2018.

    [2].    M. Moudgill, G. Nacer, C. J. Glossner, A. J. Hoane, P. Hurtley, M. Senthivelan, and P. Balzola, “Computer processor with register direct branches and employing an instruction preload structure”, 9,940,129, Issued to Optimum Semiconductor Technologies, Inc. April 10, 2018.

    [3].    M. Moudgill, G. Nacer, C. J. Glossner, A. J. Hoane, P. Hurtley, M. Senthivelan, and P. Balzola, “Vector processor configured to operate on variable length vectors using instructions to combine and split vectors”, 9,910,824, Issued to Optimum Semiconductor Technologies, Inc. March 6, 2018.

    [4].    M. Moudgill, G. Nacer, C. J. Glossner, A. J. Hoane, P. Hurtley, M. Senthivelan, and P. Balzola, “Computer processor that implements pre-translation of virtual addresses with target registers”, 9,792,116, Issued to Optimum Semiconductor Technologies, Inc. October 17, 2017.

    [5].    S. Wang, C. J. Glossner, and G. Nacer, “Opportunity multithreading in a multithreaded processor with instruction chaining capability”, 9,766,895, Issued to Optimum Semiconductor Technologies, Inc. September 19, 2017.

    [6].    C. J. Glossner, G. Nacer, M. Senthivelan, V. Kalashnikov, A. J. Hoane, P. D’Arcy, S. D. Iancu, and S. Wang, “Method and apparatus for enabling a processor to generate pipeline control signals”, 9,766,894, Issued to Optimum Semiconductor Technologies, Inc. September 19, 2017. Instruction Chaining.

    [7].    C. J. Glossner G. Nacer, M. Senthilvelan, V. Kalashnikov, A. J. Hoane, P. D'Arcy, S. D. Iancu, S. Wang, “Multithreading using an ordered list of hardware contexts”, US9558000B2. Issued to Optimum Semiconductor Technologies, Inc.

    [8].    E. Hokenek, M. Moudgill, M. J. Schulte, and C. J. Glossner, “Multithreaded processor with multiple concurrent pipelines per thread”, U.S. 8,074,051http://appft1.uspto.gov/netacgi/nphParser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearchadv.html&r=4&p=1&f=G&l=50&d=PG01&S1=glossner.IN.&OS=IN/glossner&RS=IN/glossner. Issued to Sandbridge Technologies. The instructions are pipelined in a manner which permits at least a given one of the threads to support multiple concurrent instruction pipelines.

    [9].    E. Hokenek, M. J. Schulte, M. Moudgill, and C. J. Glossner, “Processor having parallel vector multiply and reduce operations with sequential semantics”, U.S. 7,797,363http://appft1.uspto.gov/netacgi/nphParser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearchbool.html&r=1&f=G&l=50&co1=AND&d=PG01&s1=glossner.IN.&OS=IN/glossner&RS=IN/glossner, Pending for Sandbridge Technologies, Inc., A method of guaranteeing sequential semantics while executing in parallel nonassociative (saturating) arithmetic.

    [10]. E. Surducan, D. Iancu, and J. Glossner, “Microstrip multi-band composite antenna”, U.S. 7,746,276, Issued to Sandbridge Technologies, The multi-band antenna structure includes a first antenna having a band width about a middle frequency and a second antenna spaced and electrically isolated from the antenna. Ends of the second antenna are shorted to each other and the antenna floats electrically.

    [11]. M. J. Schulte, P. I. Balzola, and C. J. Glossner, “Processor reduction unit for accumulation of multiple operands with or without saturation”, U.S. 7,593,978http://appft1.uspto.gov/netacgi/nphParser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearchbool.html&r=6&f=G&l=50&co1=AND&d=PG01&s1=glossner.IN.&OS=IN/glossner&RS=IN/glossner. Issued to Sandbridge Technologies, Inc., A reduction unit that can accumulate in parallel multiple non-associative (saturating) values.

    [12]. D. Iancu, H. Ye, and J. Glossner, “Kalman filter for channel estimation in OFDM systems”, U.S. 7,573,965http://appft1.uspto.gov/netacgi/nphParser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearchadv.html&r=2&p=1&f=G&l=50&d=PG01&S1=glossner.IN.&OS=in/glossner&RS=IN/glossner. Pending for Sandbridge Technologies. A scalar Kalman filter is applied for a Least-Square estimated value for channel estimation using known pilot symbols in DVB OFDM systems.

    [13]. D. Iancu, H. Ye, J. Glossner, V. Kotlyar, and A. Iancu, “Digital implementation of analog TV receiver”, U.S. 7,483,085http://appft1.uspto.gov/netacgi/nphParser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearchadv.html&r=3&p=1&f=G&l=50&d=PG01&S1=glossner.IN.&OS=in/glossner&RS=IN/glossner. Issued to Sandbridge Technologies. An analog TV receiver implementation on DSP allows mobile platforms to view analog TV broadcasting on LCD displays.

    [14]. C. J. Glossner, E. Hokenek, M. Moudgill, M. J. Schulte, “Multi-Threaded Processor having compound instruction and operation formats”, US 7,475,222, Issued to Sandbridge Technologies. One or more of the instructions are in a compound instruction format in which a single instruction comprises multiple operation fields, with one or more of the operation fields each comprising at least an operation code field and a function field.

    [15]. C. Glossner, D. Meltzer, E. Hokenek, M. Moudgill, “Vector register file with arbitrary vector addressing”, U.S. 7,467,288 issued to IBM, A pointer array is coupled by a bus to the vector data file. The pointer array includes a plurality of entries wherein each entry identifies at least one storage element in the vector data file.

    [16]. M. J. Schulte, E. Hokenek, P. I. Balzola, and C. J. Glossner, “Arithmetic unit for addition or subtraction with preliminary saturation detection”, U.S. 7,428,567. Issued to Sandbridge Technologies, Inc. An arithmetic unit for digital signal processing capable of both 2’s complement and fixed point (saturating) arithmetic. Early detection of saturation overflow provides for faster execution unit clock rates.

    [17]. D. Iancu, H. Ye, and J. Glossner, “Iterative concatenated convolutional Reed-Solomon decoding method”, U.S. 7,370,258. Issued to Sandbridge Technologies. A method and apparatus for decoding a coded data stream of bits using an inner decoder, deinterleaver and an outer decoder.

    [18]. E. Altman, E. Hokenek, M. Moudgill, D. Meltzer, and C. J. Glossner, “System and method including distributed instruction buffers for storing frequently executed instructions in predecoded form”, U.S. 7,356,673, Issued to IBM. A system and method is provided for processing a first instruction set and a second instruction set in a single processor.

    [19]. K. Chirca and C. J. Glossner, “Arithmetic circuit with balanced logic levels for low-power operation”, U.S. 7,349,938. Issued to Sandbridge Technologies, Inc., Carry generate and propagate signals are generated to reduce the skew between stages. This reduces both dynamic switching power and short circuit power.

    [20]. D. Iancu, H. Ye, J. Glossner, and Y. Abdelilah, “Receiver with signal offset estimator and symbol synchronizing generator”, U.S. 7,346,114. Issued to Sandbridge Technologies. An OFDM receiver design for DVB.

    [21]. G. Weinberger and C. J. Glossner, “Convergence device with dynamic program throttling that replaces noncritical programs with alternate capacity programs based on power indicator”, U.S. 7,251,737. Issued to Sandbridge Technologies, Inc., Techniques for conserving power by controlling program execution in a convergence device.

    [22]. D. Iancu, J. Glossner, E. Hokenek, M. Moudgill, and V. Kotlyar, “Doppler Compensated Receiver”, U.S. 7,209,529. Issued to Sandbridge Technologies, Inc., A receiver includes a controller which receives A/D sampled input signals and shifts the sampled digital signal to compensate for Doppler effect in the input signal prior to demodulation. The controller compensates for a Doppler increased frequency by shifting the sampled digital signal.

    [23]. E. Surducan, D. Iancu, and J. Glossner, “Modified printed dipole antennas for wireless multi-band communication systems”, U.S. Patent 7,095,382. Issued to Sandbridge Technologies, Inc., A dipole antenna for a wireless communications device with gain in multiple cellular and ISM bands. August 2006.

    [24]. D. Iancu, J. Glossner, and M. Moudgill, “Rake receiver with multi-path interference accommodation”, US Patent 7, 058, 117, Issed to Sandbridge Technologies, Inc. A method of extracting data from a received signal including multipath interference in a rake receiver. June, 2006.

    [25]. E. Surducan, D. Iancu, and J. Glossner, “Modified printed dipole antennas for wireless multi-band communication systems”, U.S. Patent 7,034,769. Issued to Sandbridge Technologies, Inc., A (different) dipole antenna for a wireless communications device with gain in multiple cellular and ISM bands. April 2006.

    [26]. E. Hokenek, M. Moudgill, and C. J. Glossner, “Method and apparatus for multithreaded cache with cache eviction based on thread identifier”, U.S. Patent 6,990,557. Issued to Sandbridge Technologies, Inc. A cache memory for use in a multithreaded processor includes a number of set-associative thread caches, with one or more of the thread caches each implementing an eviction process based on access request address that reduces the amount of replacement policy storage required in the cache memory. January 2006.

    [27]. E. Hokenek, M. Moudgill, and C. J. Glossner, “Multithreaded processor with efficient processing for convergence device applications”, U.S. Patent 6,968,445. Issued to Sandbridge Technologies, Inc. A multithreaded processor with instructions for control code, digital signal processor (DSP) vector code, Java code and network processing code, and is therefore well-suited for use in a convergence device. November 2005.

    [28]. E. Hokenek, M. Moudgill, and C. J. Glossner, “Method and apparatus for thread-based memory access in a multithreaded processor”, U.S. Patent 6,925,643. Pending for Sandbridge Technologies, Inc. The multithreaded processor determines a thread identifier associated with a particular processor thread, and utilizes at least a portion of the thread identifier to select a particular portion of an associated memory to be accessed by the corresponding processor thread. August 2005.

    [29]. E. Hokenek, C. J. Glossner, A. J. Hoane, M. Moudgill, and S. Wang,, “Method and apparatus for multithreaded cache with simplified implementation of cache replacement policy”, U.S. Patent 6.912,623. Issued to Sandbridge Technologies, Inc. A cache memory for use in a multithreaded processor where an entry in a particular one of the memory locations is selected for eviction from the given thread cache in conjunction with a cache miss event, based at least in part on at least a portion of an address in an access request associated with the cache miss event. June 2005.

    [30]. E. Hokenek, M. Moudgill, and C. J. Glossner, “Method and apparatus for register file port reduction in a multithreaded processor”, U.S. Patent 6,904,511. Issued to Sandbridge Technologies, Inc. Techniques for threadbased register file access by a multithreaded processor are disclosed that use a thread identifier to reduce power dissipation. June 2005.

    [31]. D. Batten, P. G. D’Arcy, C. J. Glossner, S. Jinturkar, J. Thilo, and K. E. Wires, “Method and apparatus for reducing power consumption in a pipelined processor”, U.S. Patent 6,859,871. Issued to Agere Systems Inc. the invention evaluates the predicates of predicated instructions in a decode stage of a pipelined processor, and annuls instructions with false predicates before those instructions can be processed by subsequent stages, e.g, by execute and writeback stages. February 2005.

    [32]. E. Hokenek, M. Moudgill, and C. J. Glossner, “Method and apparatus for token triggered multithreading”, U.S. Patent 6,842,848. Issued to Sandbridge Technologies, Inc. A multithreading technique to reduce power in a processor. January 2005.

    [33]. C. J. Glossner, E. Hokenek, D. Meltzer, and M. Moudgill, “Vector register file with arbitrary vector addressing”, U.S. Patent 6,665,790. Issued to IBM. A system and method for processing operations that use data vectors each comprising a plurality of data elements. A pointer array is coupled by a bus to the vector data file. December 2003.

    [34]. D. Batten, P. G. D’Arcy, C. J. Glossner, S. Jinturkar, and K. E. Wires, “Virtual single-cycle execution in pipelined processors.” U.S. Patent 6,317,821. Issued to Lucent Technologies. A pipelined processor is configured to provide virtual single-cycle instruction execution using a register locking mechanism in conjunction with instruction stalling based on lock status. November 2001.

    [35]. D. Batten, P. G. D’Arcy, C. J. Glossner, S. Jinturkar, and K. E. Wires, “Cooperative interconnection for reducing port pressure in clustered microprocessors.” U.S. Patent 6,282,585. Issued to Agere Systems. The invention provides techniques for reducing the port pressure of a clustered processor. August 2001.

    [36]. D. Batten, P. G. D’Arcy, C. J. Glossner, S. Jinturkar, and K. E. Wires, “Duplicator interconnection methods and apparatus for reducing port pressure in a clustered processor” U.S. Patent 6,269,437. Issued to Agere Systems. The invention provides techniques for reducing the port pressure of a clustered processor. July 2001.

    [37]. C. J. Glossner, E. Hokenek, D. Meltzer, and M. Moudgill, “System and method for refreshing memory devices”, U.S. Patent 6,269,039. Issued to IBM. A method for determining if a volatile memory device needs refreshing. July 2001.

    [38]. D. Batten, P. G. D’Arcy, C. J. Glossner, S. Jinturkar, J. Thilo, S. Vassiliadis, and K. E. Wires, “Compiler-controlled dynamic instruction dispatch in pipelined processors.” U.S. Patent 6,260,189. Issued to Agere Systems. The invention provides techniques for improving the performance of pipelined processors by eliminating unnecessary stalling of instructions where a compiler groups the instructions into code blocks based on the type of pipeline dependencies that exist. July 2001.

    [39]. D. Batten, P. G. D’Arcy, C. J. Glossner, S. Jinturkar, J. Thilo, and K. E. Wires, “Shared datapath processor utilizing stack-based and register-based storage spaces.” U.S. Patent 6,256,725. Issued to Agere Systems. A processor is configured to include at least two architecturally-distinct storage spaces, such as, for example, a stack for storing control operands associated with one or more instructions, and a register file for storing computational operands associated with one or more instructions. July 2001.

    [40]. D. Batten, P. G. D’Arcy, C. J. Glossner, S. Jinturkar, and K. E. Wires, “File replication methods and apparatus for reducing port pressure in a clustered processor.” U.S. Patent 6,230,251. Issued to Agere Systems. The invention provides techniques for reducing the port pressure of a clustered processor. May 2001.

    [41]. G.G. Pechanek, L.D.Larsen, C.J. Glossner, S. Vassiliadis, "Distributed Processing Array with Component Processors Performing Customized Interpretation of Instructions." U.S. Patent 6,128,720. Issued to IBM. A multi-processor array organization is dynamically configured by the inclusion of a configuration topology field in instructions broadcast to the processors in the array. October 2000.

    [42]. C. J. Glossner, P. G. D’Arcy, S. Jinturkar, and S. Vassiliadis. "Multiple Machine View Execution in a Computer System" U.S. Patent 6,079,010. Issued to Lucent Technologies. A computer system supporting N different machine views, where N>=2, includes a memory for storing instructions, a number of execution units for processing data based on execution controls, and N different decoders for generating the execution controls using instructions retrieved from the memory. June 2000.

    [43]. G.G.Pechanek, L.D. Larsen, C.J. Glossner, S. Vassiliadis, D.H. McCabe, "Selective Processing and Routing of Results among Processors Controlled by Decoding Instructions using Mask Value Derived from Instruction Tag and Processor Identifier". U.S. Patent 5,682,491. Issued to IBM. A method describing an array of VLIW processors and dynamic reconfiguration of interconnections. October 1997.

    [44]. G.G. Pechanek, S. Vassiliadis, L.D. Larsen, and C.J. Glossner, "Array Processor Communication Architecture with Broadcast Processor Instructions." U.S. Patent 5,659,785. Issued to IBM. Communications Architecture of the Mfast processor. An 8x8 pixel-array 2-dimensional Discrete Cosine Transform (DCT) example is presented, using this invention in a folded array topology, which executes in 18-cycles. August 1997.

    [45]. G.G. Pechanek, C.J. Glossner, L. D. Larsen, S. Vassiliadis, "Parallel Processing System and Method Using Surrogate Instructions." U.S. Patent 5,649,135. Issued to IBM. Parallel VLIW Control for an Array of VLIW processors. A parallel processing system and method is disclosed, which provides an improved instruction distribution mechanism for a parallel processing array. July 1997.

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